Semiconductor ic device and manufacture thereof

Abstract

Abstract PURPOSE:To prevent the latch-up due to containing of a CMOS by a method wherein a complementary vertical type bi-polar device and a CMOS device are provided by separation of an n-epitaxial layer on a p type substrate, with p<+> layers buried by arrangement between n<+> layers, by means of p<+> layers. CONSTITUTION:The n<+> layers 3b and 3c, p<+> layer 6b surrounding their outside, n<+> layer 3a, and p<+> layer 6a surrounding its outside are formed at the boundary between the p type Si substrate 1 and the n-epitaxial layer 2', which layer 2' is then separated by providing p<+> layers 7 reaching each of the p<+> layers 6 from the surface. A vertical n-p-n transistor 30 is superposed on the n-layer on the layer 3b, and a p<+> layer 8 is superposed on the layer 3a and connected to p<+> layers 9 from the surface. Thus, a vertical type p-n-p transistor 40 with the layer 2' isolated by alienation inside the layer 7, and the layer 8 as the collector is formed. Further, a p-well 4' reaching the layer 6a is provided, and an n-MOSFET10 and a p-MOSFET20 on the layers 3a and 2 are formed. Such a construction enables the effective formation of the bipolar and CMOS elements on the same substrate by common use of the process while they keep high performance, and then the complete prevention of latch-up.

Inventors

• 👤 Hiroshi Iwasaki
• 👤 博 岩崎
• 👤 Shintaro Ito
• 👤 伊東　新太郎

Bibliographic Details