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JPS6072229A Expired / Lapsed JP ⏱️ 0.0 years remaining

Electrode and wiring structure of semiconductor device

Assignee: Hitachi Ltd
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Filing: 1983-09-28
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Granted: —
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Expires: 2003-09-28
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Abstract

Abstract PURPOSE:To avoid the generation of channeling when electrodes and wirings consisting of high-melting-point metals are arranged in a semiconductor device and impurity layers are formed by self-aligning by ion implantation using said electrodes and wirings as a mask by providing an oxide film consisting of the same metal on the metal surface before the ion implantation. CONSTITUTION:A thick SiO2 film 2 for element isolation is formed on a circumferential portion of a p type Si substrate 1 and a thin gate SiO2 film 3 is arranged on the substrate surface surrounded with said SiO2 film 2 and further the whole surface is coated with a film 4 of a high-melting-point metal such as Mo. Next, a mask 5 of a photoresist film is arranged on the substrate followed by etching using CF4 gas including O2 of 20% of leave the film 4 only in the center of surface. After that, the mask 5 is removed and a heat treatment is performed with 400 deg.C in O2 atmosphere to produce an oxide film 6 on a surface of the exposed film 4. Then this film is used as a mask to implant As ions and an implantation region 7 is formed. Thus, the ions enter deeply because atomic configurations of the metallic oxide and the metal are different and channeling is diminished.

Inventors

  • 👤 Naoki Yamamoto
  • 👤 直樹 山本
  • 👤 Seiichi Iwata
  • 👤 誠一 岩田
  • 👤 Takao Amasawa
  • 👤 天沢 敬生

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 03:02
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/011

Claims Analysis

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References Cited (Backward Citations)

JPS5863170A Cited

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