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JPS607210A Expired / Lapsed JP ⏱️ 0.0 years remaining

Double balanced mixer device

Assignee: Panasonic Holdings Corp
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Filing: 1983-06-24
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Granted: —
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Expires: 2003-06-24
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Abstract

Abstract PURPOSE:To attain low current consumption by connecting a constant current circuit to a source side without giving any effect on a high frequency signal to suppress the increase in an AC operating current attended with the increase in a local oscillating signal voltage. CONSTITUTION:In the figure, (k) is the constant current circuit, a control voltage is applied to a gate of an FET12 via a resistor 13 from a terminal (l), and a drain current of the FET12 is made constant so as to make the sum of source currents of a double balanced mixer (d) constant via a balun (c). Thus, a local oscillating signal enters the balun (a) from a local oscillating signal input terminal (e), supplied to a gate of FETs 1d, 2d, 3d and 4d and when the power is increased to >=10dBm, the current flowing to the circuit, i.e., the sum of source currents of the double balanced mixer (d) remains a slight increase within several mA to the current set by the constant current circuit (k). A high frequency signal enters the double balanced mixer (d) via the balun (c). Since the connecting point between the constant current circuit (k) and the balun (c) is grounded in terms of high frequency by a capacitor 10, the effect of the constant current circuit is avoided.

Inventors

  • 👤 Seiji Sakashita
  • 👤 坂下 誠司
  • 👤 Takeshi Sato
  • 👤 毅 佐藤

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-08 15:24
CPC Classifications
H; H03; H03D; H03D7/00; H03D7/14; H03D7/1425; H03D7/1441; H03D7/1458; H03D2200/00; H03D2200/0001; H03D2200/0023; H03D2200/0041; H03D2200/0084

Claims Analysis

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References Cited (Backward Citations)

JPS59144910U Cited

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