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JPS6072012A Expired / Lapsed JP ⏱️ 0.0 years remaining

Battery backup circuit of memory

Assignee: Toshiba Corp
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Filing: 1983-09-28
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Granted: —
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Expires: 2003-09-28
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Abstract

Abstract PURPOSE:To prevent an erroneous data from being written in a memory by delaying a reset signal, and using it as a timing for turning off a memory access signal in case when a power source is cut off. CONSTITUTION:A microprocessor 10 and an RAM11 are connected to power source lines La, Lb, and both of them execute read-out and write of a data through an address latching circuit 12, a gate circuit 13 and a bus line B. A voltage drop detecting circuit 20 is connected between said power source lines, and a detected voltage drop is held by a reset holding circuit 21, and sent to a D- type flip-flop 22 and a delaying circuit 23. In this way, a reset signal is generated by a detecting signal of a voltage drop, a transistor Q is turned off (a main power source is cut off, and a current is fed from a battery E) by making it synchronize with an ALE signal of the mircroprocessor 10, also a chip selecting signal is stop, the reset signal is delayed, and the microprocessor 10 is reset.

Inventors

  • 👤 Hiroshi Hashimoto
  • 👤 橋本 央

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-30 14:38
CPC Classifications
—

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS57117194A Cited
JPS58137021A Cited

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