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JPS6070592A Expired / Lapsed JP ⏱️ 0.0 years remaining

Writing circuit of memory

Assignee: Fujitsu Ltd
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Filing: 1983-09-28
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Granted: —
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Expires: 2003-09-28
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Abstract

Abstract PURPOSE:To expand the pulse width of a writing signal applied from the external up to a fixed value when the pulse width is narrow to write the writing signal by using potential change obtained from an output of a transistor (TR) on an input stage as an internal writing signal. CONSTITUTION:A delay type inverter DI requires a prescribed delay time td at the generation of L and H inverted outputs corresponding to H and L change of a node A1 in a node A2. The delay time td is required for the internal expansion of the width tw of an input VIN up to td when the width tw is short. When the VIN is changed to L after tw, the node A1 also tries to be changed to H. However, the potential of the node A1 is controlled by the output of an inverter I2 because a TRQ1 is turned off, so that the L level is kept until the delay time td has passed. In case of tw<td, the width tws of an internal writing signal obtained from the node A1 is expanded up to td.

Inventors

  • 👤 Atsushi Oritani
  • 👤 折谷 敦志

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-29 22:35
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS5538603A Cited
JPS5634186A Cited

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