Digital signal modulation method

Abstract

Abstract PURPOSE:To limit the consecution of a same code and also to eliminate a DC and a low frequency component by adding a slight redundancy bit in a circuit converting a data of input (2n-1)-bit into a data in 2n-bit. CONSTITUTION:The conversion of 7-bits into 8-bits is exemplified. In fig., 1 is a serial parallel converting circuit, 2 is read only memory ROM storing a conversion table, 3 is a parallel serial conversion circuit and 4 is a DSV calculating circuit. An input data is converted into a parallel data P (7-bit) by the serial parallel converting circuit 1 and this data is inputted to the ROM 2. Further, a data S representing the pluse or minus sign of an accumulated value DSV of the weight of past data is inputted to this ROM. The converted data Q and the weight R of the data are calculated and outputted based on 8 data. The converted data q is inputted to the parallel serial converting circuit 3, where the data is outputted after being converted into a serial data.

Inventors

• 👤 Moriji Izumida
• 👤 守司 泉田
• 👤 Seiichi Mita
• 👤 誠一 三田
• 👤 Akihiko Konoe
• 👤 鴻上　明彦
• 👤 Hitoshi Takagi
• 👤 均 高木
• 👤 Morihito Rokuta
• 👤 六田　守人
• 👤 Hidehiro Kaneda
• 👤 英宏 金田
• 👤 Nobuaki Fujimura
• 👤 信明 藤村
• 👤 Hiroshi Shiono
• 👤 塩野　洋

Bibliographic Details