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JPS6064472A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Toshiba Corp
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Filing: 1983-09-19
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Granted: —
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Expires: 2003-09-19
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Abstract

Abstract PURPOSE:To reduce the junction capacitance as well as to suppress the short- channel effect on the titled semiconductor device by a method wherein the third impurity layer having the impurity density higher than that of a substrate is provided on the region located directly below a part of source and drain regions. CONSTITUTION:A source region 42 and a drain region 43 are formed from the first impurity layer 341 and the second impurity layer 342 located on one side and another impurity layer 341 and the second impurity layer 342 located on the other side, and the third impurity layers 36 and 37 having the impurity density higher than that of a substrate 21 is provided on the region located directly below a part of said source and drain regions 42 and 43. As the substrate impurity density of the channel region on the MDS type transistor of this construction is not high, the boosting of VTH caused by the substrate bias is remarkably reduced. Also, the improvement of short-channel effect, the reduction in substrate current, and the improvement of a breakdown voltage can be accomplished, thereby enabling to remarkably improve the junction capacitance of the titled semiconductor device.

Inventors

  • 👤 Satoshi Shinozaki
  • 👤 篠崎 慧
  • 👤 Shizuo Sawada
  • 👤 沢田 静雄

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 00:58
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/01; H10D30/021; H10D30/0218

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS53108380A Cited
JPS5417678A Cited
JPS55151363A Cited
JPS5827369A Cited

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