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JPS6051024A Expired / Lapsed JP ⏱️ 0.0 years remaining

High speed inverter circuit

Assignee: Seiko Epson Corp
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Filing: 1983-08-30
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Granted: —
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Expires: 2003-08-30
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Abstract

Abstract PURPOSE:To invert an input signal at a high speed by constituting so that a current gain beta of each FET connected in series between potential sources is larger enough than beta of the FET for constituting one invertor, and is smaller than beta of the FET for constituting the other invertor circuit. CONSTITUTION:An input signal 502 is inputted to the gate of a P channel FET MP2 and an N channel FET MN4, and a signal 503 inverted by an invertor circuit INV1 is inputted to the gate of a P channel FET MP1 and an N channel FET MN3. Also, the signal 502 is inputted to an invertor circuit INV2, too, and an inverted signal 504 is sent to an output terminal to which the drain of an FET MN2 and MN4. In this case, each current gain value beta of the FETs MP1, MP2, MN3 and MN4 is set larger enough than a beta value of the FET for constituting the circuit INV2. Also, the beta value of the FET for constituting the circuit INV1 is set smaller than the beta value of the FETs MP1, MP2, MN3 and MN4.

Inventors

  • 👤 Nozomi Ozaki
  • 👤 望 尾崎

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-31 12:40
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01707

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