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JPS6042665A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor integrated circuit device

Assignee: Toshiba Corp
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Filing: 1983-08-19
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Granted: —
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Expires: 2003-08-19
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Abstract

Abstract PURPOSE:To facilitate the automatic generation of a test pattern by providing means which make a function logical block (supermacro) whose function is evident irrelevant logically to other circuits (composite logical circuit). CONSTITUTION:When a mode set input pin 152 is held at H, AND circuits G11- are closed, AND circuits G21- are open, and AND circuits G51- are open. A test input is passed through a shift register 9 and supplied from a test input pin 10 and an address input pin 11 to respective supermacros 2, and a test outut is sent out through an output pin 12 and a shift register 13. When a mode set input pin 153 is held at H, AND circuits G41- are opened, and the input from a composite logical circuit 3a is passed through the supermacros 2 and supplied to a composite logical circuit 3b to test the function of the circuit other than the supermacros.

Inventors

  • 👤 Takashi Yoshimori
  • 👤 吉森 崇

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-04 19:08
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/263

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS5513818A Cited
JPS5682466A Cited

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