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JPS604264A Expired / Lapsed JP ⏱️ 0.0 years remaining

Insulated gate field effect transistor

Assignee: NEC Corp
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Filing: 1983-06-22
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Granted: —
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Expires: 2003-06-22
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Abstract

Abstract PURPOSE:To attain a short channel without keeping a deep junction region too much close to a channel region, by forming a tapered side wall sufficiently thick. CONSTITUTION:The etching of an oxide film over the entire surface of a substrate by a reactive ion etching method enables to form the side wall 8 in the side surface of a polycrystalline Si. At this time, when the etching is carried out with the substrate inclined by an angle theta to the direction 10 of etchant infiltration and while it is rotated around the center axis 12, the thickness of the wall 8 increases because of being etched with taper in the shaded part. As a result, the deep junction region 9 comes off from the channel region, therefore punch through becomes difficult to occur, and the step part of the Si becomes gentle, resulting in the facilitation of fine Al wiring.

Inventors

  • 👤 Keimei Mikoshiba
  • 👤 御子柴 啓明

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-30 18:20
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60

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Total Claims: 0
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