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JPS6035537A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor integrated circuit

Assignee: NEC Corp
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Filing: 1983-08-08
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Granted: —
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Expires: 2003-08-08
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Abstract

Abstract PURPOSE:To reduce the capacity between each of signal wires by a method wherein conductive plates connected to a constant power source in low resistance are provided on the upper layer or the lower layer of a signal wire layer through an insulating layer. CONSTITUTION:A semiconductor integrated circuit is constituted of a first-layer metal wiring 2 wherein ground wires have been formed, an N type diffusion layer 3 wherein the sources and drains of transistors have been formed, a polycrystalline silicon layer 6 wherein gates have been formed, a silicon oxide film layer 7 which is used for intergate or interlayer insulation, a first passivation layer 8, a second passivation layer 9 and a silicon substrate 10. A polycrystalline silicon layer 11, whereon ground potential has been impressed, and a second-layer metal wiring layer 12, whereon ground potential has been impressed, are provided on the upper layer or the lower layer of a first-layer metal wiring layer 1 wherein signal wires have been formed. As a result, the rate of the electric lines of force, which head for the signal wires 1 and conductive plates 11 and 12, is increased, thereby enabling to reduce the capacity between each of the signal wires.

Inventors

  • 👤 Takeshi Mizukami
  • 👤 武 水上
  • 👤 Masumi Nakao
  • 👤 真澄 中尾

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 22:04
CPC Classifications
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