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JPS6028256A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Fujitsu Ltd
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Filing: 1983-07-26
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Granted: —
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Expires: 2003-07-26
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Abstract

Abstract PURPOSE:To reduce the abnormal stress applied to an element as well as to contrive an increase in housing capacity of the functional elements by a method wherein a pair of semiconductor elements are arranged in such a manner that their back sides are facing each other, and they are sealed by resin together with leads extending on to the circumference. CONSTITUTION:A semiconductor element 11 is joined to the die stage 13 of a lead frame 12, and they are connected 14 to each lead. Another semiconductor 21 is mounted on a lead frame 22 in the same manner as above, the back sides of die stages 13 and 23 are connected facing each other through an insulating spacer 6a, and a resin sealing 5a is performed thereon. As the resin 5a is formed thereon. As the resin 5a is formed symmetrical to the intermediate face of the elements 11 and 21, its stress distribution also becomes symmetrical, abnormal stress is reduced, the elements 11 and 21 can be made larger in size, and the function as a device can be increased, because two elements are housed.

Inventors

  • 👤 Rikuro Sono
  • 👤 薗 陸郎

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-06 14:59
CPC Classifications
H; H10; H10W; H10W90/00; H10W90/811; H10W72/00; H10W72/071; H10W72/075; H10W72/07551; H10W72/50; H10W74/00; H10W90/701; H10W90/751; H10W90/756

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