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JPS6020534A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device and manufacture thereof

Assignee: Hitachi Ltd
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Filing: 1983-07-15
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Granted: —
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Expires: 2003-07-15
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Abstract

Abstract PURPOSE:To perform the microminiaturization of an element and the lowering of the resistance of a wiring compatible by doping arsenic to polycrystalline silicon on an emitter in a transistor and doping either of arsenic and phosphorus or only phosphorus to polycrystalline silicon for the wiring except a section on the emitter through a self-alignment method. CONSTITUTION:A polycrystalline silicon layer 8 is formed in such a manner that non-doped polycrystalline silicon is deposited and arsenic is doped through the implantation of arsenic or polycrystalline silicon to which arsenic is doped is used. Phosphorus is diffused to the polycrystalline silicon 8 from phosphorus glass 21 through heat treatment, phosphorus is doped to the polycrystalline silicon, and polycrystalline silicon layers 8' to which phosphorus is doped are formed. Phosphorus is not doped to an emitter and the polycrystalline silicon on collector withdrawal regions 6, 7 at that time, phosphorus is not doped to an emitter region, and phosphorus can be doped to the polycrystalline silicon except a section on the emitter region in a self-alignment manner. The polycrystalline silicon is patterned, a protective oxide film 10 is shaped, and a base metallic electrode 9 is formed, thus forming a transistor.

Inventors

  • 👤 Koichi Yamazaki
  • 👤 幸一 山崎
  • 👤 Yutaka Okada
  • 👤 豊 岡田
  • 👤 Kenji Kaneko
  • 👤 金子 憲二
  • 👤 Takahiro Okabe
  • 👤 岡部 隆博

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-05 16:33
CPC Classifications
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