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JPS60179983A Expired / Lapsed JP ⏱️ 0.0 years remaining

Multi-address writing random access memory

Assignee: NEC Corp
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Filing: 1984-02-25
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Granted: —
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Expires: 2004-02-25
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Abstract

Abstract PURPOSE:To write simultaneously the same data to plural addresses by adding a multi-address writing command line and a gate circuit to an address line group and designating plural addresses at a time. CONSTITUTION:A multi-address writing command line PA is set at ''1'' and at the same time the address information inputs C-A of an address decoding part 1 is set at ''000''. Thus only an address line output (a) is set at ''1'' and outputs of OR gates 3-1-3-8 are all set at ''1''. This means that all addresses of a memory cell group 2 are designated. Under such conditions, a writing pulse is applied to a writing command terminal. Then the given data is written to all addresses. Then the line PA is set at ''1'' with the inputs C-A set at ''100'' respectively. Thus only an address line output (e) is set at ''1''. Then outputs of gates 3-1-3-4 are set at ''0'' with outputs of gates 3-5-3-8 set at ''1'' respectively. Then inputs C-A are set ''110'' and only an address line output (g) is set at ''1'', and outputs of gates 3-1-3-6 are set at ''0'' with outputs of gates 3-7 and 3-8 set at ''1'' respectively.

Inventors

  • 👤 Yasuo Ito
  • 👤 泰雄 伊藤
  • 👤 Yoshiji Furuya
  • 👤 古屋 宣二

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-08 10:42
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/12

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