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JPS60140975A Expired / Lapsed JP ⏱️ 0.0 years remaining

Control system of buffer memory

Assignee: Fujitsu Ltd
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Filing: 1983-12-27
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Granted: —
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Expires: 2003-12-27
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Abstract

Abstract PURPOSE:To facilitate transfer and control of data by setting information denoting no-signal in segment memory in a storage part at every reading of signals in segment memory when signals in buffer memory are read out. CONSTITUTION:A reading part 2 of a transmitter 1 reads out an original 3, and read-out picture signals D are stored in a transmitting buffer 4. A memory 4 consists of memory parts M1-M4 segmented into four parts. A writing control part W divides a picture signal D into four parts, and stores the 1st picture signal d1 in the memory part M1. Simultaneously it issues a control signal C and sets ''Signal 1'' in the 1st flag column F1 of a flag table 12. In the same manner, whenever the picture signals d2-d4 are stored in the memory parts M2-M4, ''Signal 1'' is set in columns F2-F4 in correspondence to the next and subsequent memory parts (M2-M4) of the flag table 12. As soon as writing is completed, the writing control part W transmits a writing completion signal WE to a control part CONT.

Inventors

  • 👤 Akio Matsui
  • 👤 昭男 松井

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 04:43
CPC Classifications
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Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS49112543A Cited
JPS56111370A Cited

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