Patent JPS5984576A successfully refreshed from Google Patents.
← Back to Patent Explorer
JPS5984576A Expired / Lapsed JP ⏱️ 0.0 years remaining

Manufacture of semiconductor device

Assignee: NEC Corp
•
Filing: 1982-11-08
•
Granted: —
•
Expires: 2002-11-08
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract PURPOSE:To prevent the junction breakdown due to the electrode formation in a thin P-N junction as well as to prevent the generation of short-circuit trouble between the adjoining electrodes by a method wherein a polycrystalline silicon (DOPOS) containing impurities is formed on the emitter aperture part only in a self-alignment manner, and said polycrystalline silicon is used as the source of diffusion. CONSTITUTION:After a base layer 5 has been formed on a semiconductor substrate 2, an emitter aperture part 3 and a base contact aperture part 4 are formed on the semiconductor substrate 2, an arsenic DOPOS layer 6 is formed and then a CVD-SiO2 film 7 is formed in the next process. Then, after a photoresist layer 10 has been spin-coated on the surface of the semiconductor, a baking is performed and when an oxygen- plasma etching is performed under the above condition, a photoresist layer 11 remains on the aperture parts 3 and 4 only. Under the above-mentioned condition, the CVD- SiO2 layer 7' on the exposed part and the arsenic DOPOS layer 6' are removed by performing an etching. Then, after the CVD-SiO4 layer of a base contact aperture part 4 and the arsenic DOPOS layer have been removed using an etching solution under the condition wherein a photoresist layer 12 is selectively formed on the upper part of the emitter aperture part 3 only, an emitter region is formed by thermally diffusing arsenic from the DOPOS 8 of the emitter aperture part 3.

Inventors

  • 👤 Hiroshi Tsuda
  • 👤 津田 博

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 12:48
CPC Classifications
H; H10; H10D; H10D48/00; H10D48/30; H10D48/32; H10D48/34; H10D48/345

Claims Analysis

Total Claims: 0
No claims parsed yet. Click Sync Now above to re-index claims from Google Patents.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag