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JPS59703A Expired / Lapsed JP ⏱️ 0.0 years remaining

Sequence control system

Assignee: Fujitsu Ltd
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Filing: 1982-06-28
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Granted: —
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Expires: 2002-06-28
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Abstract

Abstract PURPOSE:To control a device to be controlled with a microprocessor, by providing a simple hardware to the microprocessor in controlling sequentially various devices to be controlled, for attaining the instantaneous response within several tens of musec. CONSTITUTION:Sequence information to control sequentially the device to be controlled 2 with the program control of the microprocessor 1 is set to sequence control registers 41-4n via a data bus 7. When the 1st sequence control information (a) is transmitted to the device to be controlled 2 and its response information (b) is applied to a sequence control section 3, the 2nd sequence control information (c) is transmitted to the device to be controlled 2 from a sequence control information register 42 with a control signal (i). When the final sequence control information (g) is transmitted and its response information (h) is transmitted similarly, an interruption control circuit 5 transmits the interrupting signal (g) to the microprocessor 1 for completing a series of control.

Inventors

  • 👤 Shinichi Tomizawa
  • 👤 富沢 信一
  • 👤 Shigeru Nakamura
  • 👤 成 中村
  • 👤 Toru Taniguchi
  • 👤 徹 谷口
  • 👤 Yasuhiko Sasaki
  • 👤 康彦 佐々木
  • 👤 Masaaki Kurata
  • 👤 倉田 正明

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-06 12:42
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/042

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