Laminated compound semiconductor integrated circuit

Abstract

Abstract PURPOSE:To obtain a compound semiconductor laminated type IC by isolating and connecting layers by a method wherein, using a compound semiconductor of high purity for interlayer isolation of the compound semiconductir IC, a mesh form high melting point Schottky metal is buried therein, and thus the potential thereof is controlled. CONSTITUTION:N-layers 12 due to ion implantation, a W Schottky electrode 13 and a Ge ohmic electrode 14 of a thickness of approx. 1-2mum are formed on a semi-insulation GaAs substrate 11. A GaAs 151 of high purity is deposited to approx. 0.4-0.5mum at 600 deg.C or less by molecular beam epitaxial method. Next, a GaAs 152 of high purity is deposited to approx. 0.4-0.5mum via the W mesh 19, ions are implanted, thus forming the N-layers 16, and a W electrode 17 and a Ge electrode 18 are attached. When the mesh 19 is grounded with a width and an interval at 1mum or less, the high purity GaAs layer 15 becomes completely depletive, and accordingly the upper and lower IC layers are perfectly isolated. This constitution enales to easily form the laminated compound semiconductor IC by a present established technique.

Inventors

• 👤 Toshimasa Ishida
• 👤 俊正 石田
• 👤 Yoshiaki Sano
• 👤 佐野　芳明
• 👤 Yasushi Kawakami
• 👤 康 川上

Bibliographic Details