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JPS5962933A Expired / Lapsed JP ⏱️ 0.0 years remaining

CMOS data processing device

Assignee: Hitachi Ltd
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Filing: 1982-10-01
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Granted: —
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Expires: 2002-10-01
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Abstract

Abstract PURPOSE:To simplify the constitution of the device and to reduce the power consumption by applying an oscillator output to a frequency division circuit, outputting a clock pulse having different frequency from the frequency division circuit, selecting the clock pulse and operating the processor based on the selected pulse. CONSTITUTION:An LSI is formed on a substrate and the LSI is provided with a CMOS data processor 5 and an oscillating circuit 1 having an inverting amplifier A connected to a crystal oscillator X. An output of the circuit 1 is applied to a frequency division circuit 2, from which plural clock pulses having different frequency are generated and they are applied to a multiplexer 4 and a basic clock phi is transmitted selectively to the processor 5 through transmission gates MOSFETQ1-Q3. Further, a decoder 4 receives an operating mode signal C from the processor 5 and control codes C0-C2 operating selectively FETQ1-Q3 are formed with the signal C. The constitution of the MOS data processor is simplified and the power consumption is decreased.

Inventors

  • 👤 Yasushi Akao
  • 👤 赤尾 泰

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-08 14:47
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04

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