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JPS5957445A Expired / Lapsed JP ⏱️ 0.0 years remaining

Bad mark for semiconductor integrated circuit

Assignee: Mitsubishi Electric Corp
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Filing: 1982-09-27
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Granted: —
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Expires: 2002-09-27
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Abstract

Abstract PURPOSE:To facilitate the adjustment of a marker and the recognition of a defective chip, and to prevent the fouling and damage of the surface of a wafer by setting up a metallic wiring, which flows overcurrents and is blown out when a chip is defective, on the chip of the semiconductor integrated circuit. CONSTITUTION:When a tester 3 discriminates the chip as defective, an overcurrent generator 6 is operated, overcurrents are flowed through the chip through a metallic stylus on a probe card 4, and one part of the metallic wiring on the chip is burnt off. For example, two metallic pads 1A, 1'A are short-circuited previously by a metallic wiring 1B, the metallic styluses 6A, 6B on the probe card 4 are connected to each metallic pad 1A, 1'A, both poles of the overcurrent generator 6 are connected to each metallic stylus 6A, 6B, and overcurrents sufficient for burning off the metallic wiring 1B are flowed between the metallic pads 1A, 1'A. Accordingly, an acceptable semiconductor chip or a defective one can be discriminated by the presence of the metallic wiring 1B.

Inventors

  • 👤 Teruaki Harada
  • 👤 原田 輝昭

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-02 14:40
CPC Classifications
H; H10; H10P; H10P74/00

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Total Claims: 0
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