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JPS595481A Expired / Lapsed JP ⏱️ 0.0 years remaining

Flag controlling system of stack memory control

Assignee: Fujitsu Ltd
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Filing: 1982-06-30
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Granted: —
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Expires: 2002-06-30
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Abstract

Abstract PURPOSE:To reset effective flag of the block of a high speed buffer using simple configuration, by performing interruption basing on the shrinkage flag that responds to exceeding of block boundary of a high speed buffer memory in the direction of shrinking of a stack. CONSTITUTION:Set operation code is interpreted by an operation code decoder 2, and in case of direction of shrinking of a stack, output l1 of the decoder 2 becomes high level. When the address necessary for selection of a multiplexer 3 exceeds blocks B0, B1- of a high speed buffer memory B, output l2 of a comparator 4 is inverted to high level through a pointer HST, and shrinkage flag S from an AND gate 6 becomes high level and a processer 15 is interrupted. The flag of the bit that forms tag of corresponding blocks B0, B1- is reset by simple configuration using a shrinkage flag.

Inventors

  • 👤 Takeshi Shinoki
  • 👤 剛 篠木
  • 👤 Akira Hattori
  • 👤 彰 服部

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-24 16:06
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08

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