Mos type semiconductor device and manufacture thereof

Abstract

Abstract PURPOSE:To realize a miniaturized device of high density, by forming C- MOSFET in a three-dimensional manner and by connecting gate electrodes in common. CONSTITUTION:A p well 12 is provided on an n type Si substrate 11, and an n<+> layer 13 is formed on the surface of the p well 12, while p<+> 14 is formed on the surface of the substrate 11. Next, an epitaxial layer 15 being superposed, a p well 16 is formed in contact with the well 12 and an n<+> layer 17 is formed on the surface of the well 16, while a p<+> layer 18 is formed thereon. Parts of the layer 15 and the substrate 11 including parts of the layers 13, 14, 17 and 18 are etched to make a hole 19, and an insulating film 20 for separation is buried at the bottom of the hole. Next, the entire surface and the wall of the hole are covered with a gate insulating film 12, and a gate electrode 22 is buried in the hole 19. Thus, n-ch FET is constituted by the layers 13 and 17 and the electrode 22 and p-ch FET by the layers 14 and 18 and the electrode 22, and when the layers 13 and 14 are connected, a C-MOS inverter is constituted. Since n- and p- channel FETs are constituted oppositely and three-dimensionally through the intermediary of the same gate electrode, an area occupied by the device can be reduced remarkably.

Inventors

• 👤 Masashi Wada
• 👤 和田　正志

Bibliographic Details