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JPS5921072A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor nonvolatile memory device

Assignee: Mitsubishi Electric Corp
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Filing: 1982-07-26
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Granted: —
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Expires: 2002-07-26
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Abstract

Abstract PURPOSE:To compose a memory of a channel and a gate by a method wherein a part of a memory gate is made to have the function of a control gate, and only a channel region functions as an MNOS memory transistor and a control transistor, in an MNOS structure. CONSTITUTION:Write is performed by impressing a positive high voltage on a memory gate 7a and earthing an n type Si substrate 1, a p-well 2, and a Z region 5. A high electric field is applied between the memory gate 7a and the p-well, electrons transfer from the p-well 2 to the direction of the memory gate 7a through an SiO2 film 9 by tunnel phenomenon, and trapped by the electron capture center in the neighborhood of the boundary surface between the SiO2 film 9 and an Si3N4 film 8, resulting in finish of write. Next, erasure is performed by earthing the memory gate 7a so that the electric field in reverse direction to that of write and impressing a positive high voltage on the p-well 2. The electron trapped by the electron capture center in the neighborhood of the boundary surface between the SiO2 film 9 and the Si3N4 film 8 return to the p-well 2 through the SiO2 film 9 by tunnel phenomenon, resulting in finish of erasure.

Inventors

  • 👤 Ryuichi Matsuo
  • 👤 龍一 松尾

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-05 15:10
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/69

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