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JPS59207641A Expired / Lapsed JP ⏱️ 0.0 years remaining

Integrated circuit

Assignee: Hitachi Ltd
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Filing: 1983-05-11
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Granted: —
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Expires: 2003-05-11
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Abstract

Abstract PURPOSE:To reduce the size of a chip, by constituting a power feeding pattern by main line patterns extended from a bus line pattern into wiring regions between blocks and branch patterns extended to block feeding points from the main line patterns. CONSTITUTION:On a semiconductor chip 10 formed in a rectangular shape, blocks 14-1-14-9 are arranged. A rectangular bus line pattern 16 is formed so as to surround the blocks 14-1-14-9. The blocks 14-1 is constituted by cells 12-1 and 12-2. The other blocks 14-2-14-9 are similarly constituted. Power distributing patterns 18-1 and 18-2 of each block are not formed to be extended out of the region of the block but formed to power feeding points 22-1-22-4 at block- boundary positions. Therefore, even though blocks having different sizes are arranged depending on the functions, the layout of the blocks can be optimized and the chip size can be reduced.

Inventors

  • 👤 Toshiyuki Yamakami
  • 👤 山神 俊行

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-08 15:10
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/211

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