Semiconductor integrated circuit device

Abstract

Abstract PURPOSE:To obtain a C-MOS.IC having high latch-up resistance by a method wherein an n<+> type buried layer is formed partially to the surface layer section of an n<--> type Si substrate, an n<-> type layer is grown on the whole surface containing the buried layer in an epitaxial manner, the epitaxial layer on the buried layer is used as one transistor forming region, a p<-> type layer is shaped to the epitaxial layer, which does not contain the buried layer, and the p<-> type layer is used as the other transistor forming region. CONSTITUTION:An n<+> type buried layer 113 is diffused and formed to the surface layer section of an n<--> type Si substrate 105, and an n<-> type layer 105a is grown on the whole surface containing the buried layer 113 in an epitaxial manner. A p-n-p transistor 2 is shaped into the layer 105a positioned on the layer 113, a p<-> type region 106 is diffused and formed into the layer 105a, which does not contain the buried layer 113, and an n-p-n transistor 3 is formed in the region 106. Accordingly, base concentration in the two transistors can be elevated, the number of recombination of carriers in bases augments, a current amplification factor lowers, and latch-up resistance increases.

Inventors

• 👤 Yukio Miyazaki
• 👤 行雄 宮崎

Bibliographic Details