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JPS59200449A Expired / Lapsed JP ⏱️ 0.0 years remaining

Lead frame for semiconductor device

Assignee: NEC Yamagata Ltd
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Filing: 1983-04-28
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Granted: —
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Expires: 2003-04-28
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Abstract

Abstract PURPOSE:To reduce an effect on a lead for an external lead-out generated on a cutting by separating the end surface of a clearance in an outer frame from the extension of the central line of the lead for the external lead-out. CONSTITUTION:A clearance 25, an end surface 251 thereof does not coincide with the extension of the center 27 of a lead 23 for an external lead-out, is formed to an outer frame section 22. Accordingly, possibility resulting in the deformation of the lead 23 for the external lead-out can be inhibited even when strain on processing in a cutting 26 is generated in the end surface 251 of the clearance 25.

Inventors

  • 👤 Shunichi Kon
  • 👤 近 俊一

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-08 21:55
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/40

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