Gate array with memory

Abstract

Abstract PURPOSE:To readily obtain a memory of desired unit configuration in response to the usage and utility by dividing a chip into two parts, disposing a gate array of only transistor array on one side, disposing a memory block on the other side to obtain a memory block having an arbitrary bit and word unit. CONSTITUTION:A memory unit 11 made of memory blocks 11A, 11B, 11C, 11D and a transistor array 12 are arranged on an area of approx. 1/2 on a gate array chip 10. The memory unit 11 can read/write the stored content corresponding to addresses 0-7 by an address decoder 21 associated similarly to an address decoder 22. The output of the decoder 22 becomes a select signal corresponding to a selector 23 which selects the output data from the memory unit 11 and outputs it to a memory data line NDL. The wirings to the array unit 12 are performed in the steps in which the entire logic is determined and the personalization of the chip is formed.

Inventors

• 👤 Tsuneo Kinoshita
• 👤 常雄 木下

Bibliographic Details