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JPS5918679A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Fujitsu Ltd
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Filing: 1982-07-22
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Granted: —
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Expires: 2002-07-22
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Abstract

Abstract PURPOSE:To improve the reproducibility of characteristics of a semiconductor device and to reduce the rate of defects by forming different impurity densities of semiconductor regions which are contacted with a gate electrode from those of regions which are contacted with source and drain electrodes. CONSTITUTION:A no-addition GaAs buffer layer 12 and an N type layer 13 of 105X 10<17>cm<-3> in density are epitaxially formed on a semi-insulating GaAs substrate 11, and an AlN film 14 is superposed. Three-layer mask of photoresist 16, Ti 17 and Au 18 is formed on a region 15 to be formed with the gate electrode of an enhancement type FET, O ions are implanted by energy in the prescribed density, and the region is annealed at 600 deg.C for 20min. Since the annealing is performed at the temperature lower than the conventional annealing, no thermal deterioration occurs in a substrate. Then O ions are implanted to 1/2 or more of the thickness of the layer 12 in multistage, the mask is removed, and source electrodes 20, 21 of AuGe/Au, drain electrodes 22, 23 and gate electrodes 24, 25 of Ti-Pt-Au are formed as the conventional one. Since ion implantation is limited to the part directly under the gate electrode and low temperature treatment is performed, the source, drain and channel are maintained in preferable state of epitaxial layer, thereby improving the reproducibility of various characteristics and reducing the rate of defect.

Inventors

  • 👤 Koichiro Kotani
  • 👤 小谷 紘一郎
  • 👤 Takashi Mimura
  • 👤 高志 三村

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 06:04
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80

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