Semiconductor integrated circuit device

Abstract

Abstract PURPOSE:To improve withstanding voltage and to prevent yielding of parasitic elements, by forming an element separating layer, which reaches a p<+> layer from an n layer in a p<+>n-n<+>n constitution, providing the p<+> layer as a channel stopper, providing an n<+> layer for reducing collector resistance, and providing a bipolar element in the n layer. CONSTITUTION:On a p<+> type Si substrate 31, a p layer 32, an n<+> layer 33, and n layer 34 are sequentially laminated. Etching is performed, and grooves reaching the p<+> substrate 31 are formed and filled up with poly Si 35. Then, an n<+> layer 36 is selectively formed by ion implantation. Thereafter, p layers 37-39 and an n layer 40 are formed. Finally, the surface is coated by SiO2 42, and an Al electrode 41 is provided. Thus the device is completed. In thid constitution, channel prevention is performed by the substrate 31. The p<+> substrate and the n<+> layer 33 are separated by the p layer 32 in the vertical direction. Therefore, withstanding voltage is not deteriorated. Since the n<+> layer 33 is uniform, hFE of parasitic p-n-p caused by the layers 37-34-33-32 is 0.1 or less due to the high concentration of the n base 33, and no actual obstacle is yielded. A mask process can be also reduced.

Inventors

• 👤 Toyoki Takemoto
• 👤 竹本　豊樹
• 👤 Tsutomu Fujita
• 👤 勉 藤田
• 👤 Hiroyuki Sakai
• 👤 坂井　弘之
• 👤 Kenji Kawakita
• 👤 川北　憲二

Bibliographic Details