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JPS589476A Expired / Lapsed JP ⏱️ 0.0 years remaining

Controller of digital key signal

Assignee: Sony Corp
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Filing: 1981-07-09
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Granted: —
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Expires: 2001-07-09
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Abstract

Abstract PURPOSE:To control the timing of an edge part at an optional value, by detecting the front and rear edges of a digital key signal and enlarging or compressing of the data of each detection by a prescribed degree based on an indication. CONSTITUTION:A digital key KEY is supplied to a shifting/rough control circuit 38 and then fed to a fine control circuit 39. These circuits 38 and 39 are controlled by a control logical circuit 40 which receives the supply of the data and the control signal from a microprocessor. Then the front and rear edges of the signal KEY are enlarged and compressed at every sampling period and by the outputs of the RAM42-44 that prescribe the degree of enlargement and compression of the edge of the circuit 38 and a level comparator 45 that detects the front and rear edges of the signal KEY. Then the signal received a rough control is fed to the circuit 39 including a buffer memory 57 plus RAM58 and 59. Thus both edges are enlarged or compressed within a clock period.

Inventors

  • 👤 Yoshikazu Yamamoto
  • 👤 嘉一 山本

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 13:13
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/64; H04N9/74; H04N9/75

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS5315022A Cited
JPS5418621A Cited
JPS55143876A Cited

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