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JPS5892265A Expired / Lapsed JP ⏱️ 0.0 years remaining

Manufacture of semiconductor device

Assignee: Fujitsu Ltd
•
Filing: 1981-11-27
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Granted: —
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Expires: 2001-11-27
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Abstract

Abstract PURPOSE:To improve characteristics and the like, by forming a gate electrode by materials having a low resistivity and the like, with respect to an FET, with the alignment of the gate electrode and an ion implantation region being kept equivalent with a self-aligning method. CONSTITUTION:A gate pattern 6 is formed with the first material layer on an semi-insulating GaAs substrate 1. With the pattern as at least a part of a mask, the ion implantation is performed. An insulating film 10 is deposited and formed on a wafer. Thereafter, the pattern 6 is selectively removed together with the insulating film 10 thereon. Thus openings, in which a gate pattern is to be formed are provided. A heat treatment is performed to activate the implanted ions. Thereafter, the gate electrode, which has a multiple layer structure made of a material having a low resistivity or the combination of the materials as the second material, is formed. Thus the characteristics and reliability are improved.

Inventors

  • 👤 Shigeru Okamura
  • 👤 茂 岡村

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-04 13:55
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS5860574A Cited

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