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JPS5883377A Expired / Lapsed JP ⏱️ 0.0 years remaining

Buffer memory control system

Assignee: Fuji Electric Co Ltd
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Filing: 1981-11-09
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Granted: —
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Expires: 2001-11-09
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Abstract

Abstract PURPOSE:To increase the hit rate to a program and to optimize main storage area allocation dynamically by measuring the use frequency and hit rate of every segment, and altering the allocation of a main storage area according to the measured results. CONSTITUTION:An address register 1 is equipped with a block number specification part 11 stored with keys for retrieving whether a reference block resides in a buffer memory 6 or not, a set number specification part 12, and an in-block relative address specification part 13. Then, the storage area in a main storage device 7 is divided into segments, and the storage area in the main storage device 7 are allocated to the respective segments; and a CPU measures reference frequencies and hit rates corresponding to the segments, and the allocation of the storage area of the main storage 7 to the segments is altered dynamically according to the measured results, the kind of the program, or the both.

Inventors

  • 👤 Yasuyuki Obara
  • 👤 小原 康幸
  • 👤 Masami Takada
  • 👤 正美 高田

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-03 19:46
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802

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