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JPS5871775A Expired / Lapsed JP ⏱️ 0.0 years remaining

Level stabilizing circuit

Assignee: Sony Corp
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Filing: 1981-10-26
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Granted: —
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Expires: 2001-10-26
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Abstract

Abstract PURPOSE:To ensure the accurate stabilization of levels and to simplify the constitution of a level stabilizing circuit, by inserting reference signals having the reference levels corresponding to black and white levels into a TV signal and controlling these reference signals with a common circuit so that they are set at a constant level. CONSTITUTION:The reference signals S1 and S2 are set at a reference level E1 corresponding to a black level and at a reference level E2 higher than the level E1 by DELTAE. A TV signal SV to which the signals S1 and S2 are inserted is supplied to a video output circuit 40 via an AGC circuit 20 and a control circuit 30 for DC bias. A part of the video output is supplied to a level control circuit 60 to perform the control so that the level difference between signals S1 and S2 is always constant. Furthermore a level control circuit 70 performs the control so that a beam current IK flowing to a CRT 50 when the signal E2 is inserted is set at a constant level. Therefore the level difference DELTAE is set constant by the circuit 60, and the level E2 is set constant by the circuit 70. As a result, both black and white levels are controlled at one time and can be stabilized.

Inventors

  • 👤 Kazuo Koizumi
  • 👤 小泉 和雄

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-03 21:46
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/14; H04N5/16

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