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JPS5866352A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor integrated circuit and manufacture thereof

Assignee: Seiko Instruments Inc
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Filing: 1981-10-16
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Granted: —
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Expires: 2001-10-16
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Abstract

Abstract PURPOSE:To enable to form the optimum well as well as to obtain the IC on which various types of transistors are mounted by a method wherein a p-well is provided on the p<-> epitaxial layer located on a p type substrate and an n-well is provided at the upper part of the p-well and an n<+> buried layer, and n-MOS is formed in the p-well, and junction type and p-MOS are formed in the n-well. CONSTITUTION:The p-wells 4, 14 and n-wells 5, 15 are formed on the n<-> epitaxial layer 3 on the p type substrate 1 having an n<+> buried layer 2, and an isolated or buried electrode is formed by p-layers 6, 16 and n-layers 7, 17. Then, an-channel MOSQ1 is formed on the p-well 4, a p-channel MOSQ2 is formed on the n-well 5, a p-n-p horizontal type BJTQ4 is formed on the n-well 15, and an n-p-n vertical type BJTQ3 is formed on the p-well 14. According to this constitution, as n<+> buried layer is located at the bottom of the n-well 5, latch up is prevented and the epitaxial layer is formed extremely thin, and the integration density can be easily improved. Also, as the p-well 14 was formed deeply, both hFE and low threshold voltage can be obtained. Since the density of wells can be freely selected from the optimum value of various types of transistors, a high density mounting can be performed.

Inventors

  • 👤 Masafumi Shinpo
  • 👤 新保 雅文

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-29 06:54
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038

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