Reducing method for switching loss of high frequency inverter

Abstract

Abstract PURPOSE:To reduce a switching loss of a high frequency inverter by selecting a rectangular switching frequency fr to the range of fs/fr=1.1-1.4 to a resonance frequency fs and displacing the period from the current stopping time of a switching element to the voltage generating time by the prescribed time. CONSTITUTION:A series resonance circuit of a resonance frequency Fs having a capacitor 3 and an inductance 4 is formed, a rectangular switching frequency fr to be applied to semiconductor switching elements 1, 2 is set to the range of fs/fr=1.1-1.4, and the period from the current stopping time to the voltage generating time of the elements 1, 2 is displaced by the prescribed time. In this manner, the charging current, discharging current and load current flowing through the capacitor 3 become I1, I2, IL, can be maintained at the prescribed value in the range of fs/fr=(tc+ts)/tc=1.1-1.4, and the switching loss at the switching closing time can be reduced to zero.

Inventors

• 👤 Akira Dobashi
• 👤 明 土橋
• 👤 Hideo Yazawa
• 👤 秀夫 矢沢

Bibliographic Details