Data transmitter and receiver

Abstract

Abstract PURPOSE:To secure the justice of data and to protect a system, by disusing the data block when a data receiver detects the injustice of the sequence number, a check code and a step-out. CONSTITUTION:If a step-out is detected at a serial-parallel converting part, the output of a terminal 1 is set at ''1''. In the normal working mode, the outputs of both an inverter circuit 28 and an AND circuit 24 are set at ''1''. And the output 33 of a flip-flop circuit 22 is set at ''1''. If a step-out is detected, the output of the circuit 28 is set at ''0''. Then the state of the circuit 22 varies, and the output of the circuit 22 is set at ''0''. As a result, a counter 31 is reset, and the output of a terminal 9 is never set at ''1''. Therefore the writing timing is not informed to a buffer control part for the input data of a terminal 4. This prevents the writing of data to a buffer. That is, the data block is disused.

Inventors

• 👤 Yoshinobu Miyano
• 👤 栄伸 宮野
• 👤 Hideo Suzuki
• 👤 英男 鈴木

Bibliographic Details