Semiconductor memory circuit

Abstract

Abstract PURPOSE:To prevent the range of reference potential setting from being decreased at high temperatures, by providing a negative temperature coefficient to a load resistance value of a memory cell using a multi-emitter transistor (TR). CONSTITUTION:A memory cell is constituted by connecting a parallel connection of a Schottky barrier diode D and a load resistor Rc to a multi-emitter TR Qc1. Through the provision of a negative temperature coefficient for the load resistor Rc used for the memory cell, the reduction in the set range of a reference potential VR at high temperatures can be prevented for stable operation.

Inventors

• 👤 Joji Nokubo
• 👤 野久保　丞二
• 👤 Masahiko Arimura
• 👤 有村　政彦

Bibliographic Details