Memory data line precharge circuit

Abstract

Abstract PURPOSE:To perform stable memory operation, by shortening first data line pairs at the start of precharge for data lines and then performing the precharge of the data line pairs to the power supply voltage. CONSTITUTION:At memory operation, a transistor (TR) Q11 is activated with a control signal phi5 of high level at the start of precharge and charges on a data line DL are discharged to ground, through the TRQ11. After short-circuit of the data line pair DL, an input signal phi4 goes to high level and a level of a node N4 is further increased through the capacitance coupling between a drain electrode of a TRQ9 and the gate electrode N4, to which the input signal phi4 is supplied. Thus, the node N2 is charged. When a boosting signal phi3 rises with a little delay from the leading of the input signal phi4, the level of the node N2 is boosted to a level, a power supply voltage Vcc or over with a bootstrap capacitance C2.

Inventors

• 👤 Yasunori Yamaguchi
• 👤 山口　泰紀

Bibliographic Details