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JPS5832178A Expired / Lapsed JP ⏱️ 0.0 years remaining

Ic tester

Assignee: Advantest Corp
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Filing: 1981-08-19
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Granted: —
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Expires: 2001-08-19
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Abstract

Abstract PURPOSE:To make the skew quantity among test pattern signals zero by providing a phase comparing means on the signal output side to permit measurement of the phase differences among the outputted test pattern signals and setting delay times with a variable delaying circuit. CONSTITUTION:Disconnecting means 21, 22 are provided between a driver group 8 and an IC9 to be tested, and between the element 9 to be tested and a logical decision circuit 11. With respect the IC of the kind to be tested for the first time, said IC is disconnected in a calibration mode, and the delay times of variable delaying circuit groups 7 and 16 are calibrated. On the other hand, while the means 21, 22 are held disconnected, a phase comparing means 25 is connected to the output side of a driver group 8 by a switch 23, and a signal source 26 is connected to the input side of a logical comparator group 11 by a switch 24. The signal having the reference phase of the test pattern signal is applied to the means 25 from a timing signal generator 1, and is compared of phase with the signals outputted from the driver group 8. The results are made into the control signal for the group 7 via a microcomputer 18, and act so as to make the skew quantity among the signals zero.

Inventors

  • 👤 Shigeru Sugamori
  • 👤 茂 菅森

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 08:50
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31903; G01R31/31908; G01R31/3191

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS6222103A Cited

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