Control circuit of signal transmission time

Abstract

Abstract PURPOSE:To increase a time margin of DIN input in a writing mode, by varying the transmission time of input signal within a logical circuit of another input signal between the generation and the erasion of an input signal of a logical circuit having >=2 input terminals. CONSTITUTION:A signal phi1 has the same phase as an input signal WE and has a delay by time T1. This signal phi1 is kept at a high level during time, T1, and therefore the conductance is large for MISFETQ53 and Q56 respectively. Then contacts N52 and N54 are charged and discharged earlier than a time constant. As a result, a signal DIN is quickly transmitted to a contact N55. On the contrary, the signal phi1 is set at a low level if the writing mode is kept long. Thus the signal DIN is slow to be transmitted to the contact N55. Thus the time T0 is short immediately after writing and can be increased at the end of writing. As a result, the writing time of an output DIN can be set long to an effective data. This increases a time margin.

Inventors

• 👤 Koji Ozawa
• 👤 小沢　孝司

Bibliographic Details