Semiconductor memory circuit

Abstract

Abstract PURPOSE:To shorten the writing time by inhibiting the operation of the delay circuit when the writing is carried out. CONSTITUTION:MISFETQ69 to which control signal r/w is applied in parallel plus MISFETQ71 and MISFETQ70 which feature the low levels at the non-set time in series to MISFETQ69 with application of Y address information ay0 featuring the opposite phases to each other at the set time are provided to MISFETQ67 forming delay circuit. And at the writing time, output timing signal YWC of the Y address decoder is delivered at the moment when the Y address information is set regardless of the output timing signal XWC of the X address decoder and the operation of the delay circuit. As a result, the writing action cycle can be shortened.

Inventors

• 👤 Tsuneo Ito

Bibliographic Details