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JPS58182A Expired / Lapsed JP ⏱️ 0.0 years remaining

semiconductor equipment

Assignee: Seiko Epson Corp
•
Filing: 1981-06-25
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Granted: —
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Expires: 2001-06-25
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Abstract

Abstract PURPOSE:To obtain an isolating region with a smooth surface free of crystal defects by a method wherein the isolating region is constituted of a two layer structure consisting of a polycrystalline semiconductor region and an insulator region, in a process for the establishment of an element isolating region on a monocrystalline substrate constituting a MOS type semiconductor device. CONSTITUTION:A P type or N type Si substrate 1 is coated with an Si3N4 film 2 and an opening is provided at a place corresponding to the element isolating region. A groove is formed in the substrate 1 exposed in the opening by the anistropic or ion etching method. Next, the entire surface including the groove is coated with a polycrystalline Si layer 3 by the CVD method. The layer 3 in the groove is not in contact with the layer 3 on the film 2. Elements separating field ions are then implanted. By using the CVD method, an SiO2 film 5 is grown, again the part in the groove not in contact with the other part. The heat generated in this CVD process causes the layer 3 within the groove to diffuse ions to the surrounding groove wall for the formation of a diffused layer 6. Next, the entire surface is covered with a resist film 7, which is followed by a reactive ion etching process wherein the film 5 is removed together with the film 7. Further, the layer 3 and the film 2 on the substrate surface are removed, with the portions of the film 5 and the layer 3 in the groove only surviving the dismantling process.

Inventors

  • 👤 Juri Kato
  • 👤 樹理 加藤

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 03:14
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS5432984A Cited

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