Data transfer controller

Abstract

Abstract PURPOSE:To make it possible to transfer easily data even to a memory of large capacity, by carrying out both reading and writing of the memory simultaneously and independently of each other. CONSTITUTION:A data transfer controller consists of an address generating part 4, a read/write controlling part 2, a memory access region controlling part 5 and a memory controlling part 3. The part 3 receives a read/write indicating signal and data showing a memory access region from a CPU, for instance, and then applies a start address to the part 4 for a memory access. At the same time, the part 3 gives both word length and address length of the region to which access should be given to the part 5 and furthermore gives a read/write start signal to the part 2. Then the part 2 delivers a transfer end signal to the part 5 every time one-cycle transfer of data is over, and the transfer end signal is transmitted to the control part 3.

Inventors

• 👤 Chiaki Motegi
• 👤 茂手木　千秋

Bibliographic Details