High-speed fixed number arithmetic circuit

Abstract

Abstract PURPOSE:To reduce memory capacity without extending arithmetic time, by dividing a memory table into a high-order and a low-order digit area. CONSTITUTION:A multiplying circuit consists of a high-order digit table memory 12 which has address areas each corresponding to 256 multiplicands and multiplier areas for multipliers corresponding to high-order digit 8-bit multiplicands, a low-order digit table memory 13 which has address areas corresponding to multiplicands 1-255 and multiplier areas for multipliers corresponding to said multilpicands, and an addition part 9 which sums up and output arithmetic results of those high-order and low-order digit table memories 12 and 13. Consequently, the high-order digit table memory 12 stores multipliers corresponding to every multiplicands 256-256 and the low-order digit table memory 13 stores multipliers corresponding to multiplicands 1-255, so the memory capacity is reduced greatly.

Inventors

• 👤 Seiichiro Watanabe
• 👤 渡辺　誠一郎
• 👤 Hiroyuki Takeuchi
• 👤 博幸 竹内

Bibliographic Details