Semiconductor logic circuit

Abstract

Abstract PURPOSE:To improve integration while decreasing the inverter area on the surface of a substrate by forming a load resistor and a junction type field effect transistor in laminated relation in a substrate of a semi-insulative semiconductor. CONSTITUTION:An N type conductive layer 3 is formed on the main surface 2 of a semiconductor substrate having semi-insulative Ga As and a conductive layer 4, which is longer than the N type conductive layer 3, is laminated with its end aligned with the end of the N type conductive layer 3 by N type impurity ion injection. An N<+> type conductive layers 5, 6, 7 are connected to the conductive layer 3 and the conductive layer 4 each having a common conductive layer 6. A gate electrode 11 which has a Schottky junction 12 is formed in the middle of the conductive layer 3. A load resistor L is connected to the drain of a driving transistor M thus making the area occupied by the circuit small.

Inventors

• 👤 Kazunori Yamamoto
• 👤 Masamichi Omori

Bibliographic Details