Patent JPS5789253A successfully refreshed from Google Patents.
JPS5789253A
Expired / Lapsed
JP
⏱️ 0.0 years remaining
Semiconductor device
Assignee: Seiko Epson Corp
•
Filing: 1980-11-25
•
Granted: —
•
Expires: 2000-11-25
Abstract
Abstract PURPOSE:To decrease punching through by providing a multi-crystal Si layer between metal wiring and a diffusion layer of an MOSFET. CONSTITUTION:A gate oxide film 103 is formed on an Si substrate having a field oxide film 102 and a source drain regions. And a multi-crystal Si electrode 104 is also formed and, through an interlayer insulation film 106, metal wiring 107 is formed. This decreases a stage difference preventing a short circuit due to a misfitting at the time of photo etching and also controls punching-through that short circuits the substrate and the metal wiring below it.
Inventors
- 👤 Toshihiko Kondo
Bibliographic Details
Application Number
—
Jurisdiction
JP
Data Source
google_patents
Last Synchronized
2026-11-08 19:56
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60
Claims Analysis
Total Claims: 0
No claims parsed yet. Click Sync Now above to re-index claims from Google Patents.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.