Manufacture of semiconductor device

Abstract

Abstract PURPOSE:To reduce the area of an element isolation region of semiconductor device by a method wherein a concave and convex regions are formed in a magnesia spinel layer, and after a single crystal semiconductor layer is formed on the region thereof, the single crystal semiconductor layer is removed up to expose the magnesia spinel layer. CONSTITUTION:The magnesia spinel layer 10 is formed on a single crystal silicon substrate 2, the concave and convex regions 11, 12 are formed in the layer 10 mentioned above, and after the silicon epitaxial layer 13 is formed thereon, the silicon epitaxial layer 13 grown upwardly from the magnesia spinel layer 10 is polished by chemical polishing to expose the magnesia spinel layer 10, and source and drain regions 3, 4 and a gate 5 are formed in the magnesia spinel layer 10 thereof. Accordingly the element isolation region can be formed easily, and isolation breadth a of an intergrated circuit can be determined by the breadth of the magnesia spinel layer whose etching off is not performed when patterning is to be performed.

Inventors

• 👤 Masaru Ihara
• 👤 Yoshihiro Arimoto

Bibliographic Details