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JPS5776925A Expired / Lapsed JP ⏱️ 0.0 years remaining

Mos type circuit

Assignee: Toshiba Corp
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Filing: 1980-10-29
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Granted: —
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Expires: 2000-10-29
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Abstract

Abstract PURPOSE:To decrease the power consumption at stand-by, by providing an MOSFET between a gate common connecting point of a complementary MOS inverter and input and power supply terminals. CONSTITUTION:The drain of a P channel MOSFETT3 and the drain of an N channel MOSFETT4 are connected to an input terminal 11 of a C-MOS inverter, and the source of the MOSFETT4 is grounded. The gates of the both FETs are connected in common, and a signal of L level is applied at the use of the C-MOS inverter and a signal of H level is applied at stand-by. At stand-by, the FETT3 is nonconductive and the T4 is conductive, and a signal applied to a terminal 13 is not delivered to the input terminal 11 of the C-MOS inverter. In this case, since the terminal 11 is held at L level, an FETT1 is nonconductive and a current flowing to the both FETs does not flow to the C-MOS inverter.

Inventors

  • 👤 Katsuhiko Sato

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-31 09:40
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0008; H03K19/0016

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Total Claims: 0
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