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JPS5776915A Expired / Lapsed JP ⏱️ 0.0 years remaining

Logical circuit for trigger control

Assignee: Oki Electric Industry Co Ltd
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Filing: 1980-10-30
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Granted: —
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Expires: 2000-10-30
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Abstract

Abstract PURPOSE:To execute inverting operation surely, by adding the information of unfinished inverting operation of a flip-flop circuit to a trigger signal generating means and widening the pulse width of a trigger signal. CONSTITUTION:A trigger signal 7 is formed 103 by an output 5 of a D type flip- flop 101 taking an input signal 1 and a clock signal 2 as input and an inverting clock 6. The trigger signal 7 triggers an FF105 via an AND gate 104. On the other hand, an output 8 of the AND gate 104 is applied to a suppression input terminal of an NAND gate 300 with suppression type input terminal, and since and output 10 of the NAND gate 300 is kept to L level until the inverting operation of an FF105 is finished, the pulse width of the trigger signal 7 is widened. When the inverting operation of the FF105 is finished, the output of the NAND gate 300 is at H level, and the trigger input of a flip-flop 105 is absent.

Inventors

  • 👤 Takafumi Shimizu

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-08 09:44
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037

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