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JPS5776604A Expired / Lapsed JP ⏱️ 0.0 years remaining

Numeric controller

Assignee: Fanuc Corp
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Filing: 1980-10-30
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Granted: —
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Expires: 2000-10-30
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Abstract

Abstract PURPOSE: To shorten a processing time by performing bit-by-bit operation instead of byte-by-byte or word-by-word operation when executing instructions of a general microprocessor. CONSTITUTION: In a readout cycle, a selector SE1 outputs data, read out of an RAM and having bits "0", "1", "0", and "0" as its high-order four bits, to the data bus 2 of a CPU. In a write cycle, on the other hand, a register RE stores data of an address consisting of the specific high-order four bits. Then, data outputted to the specific bit line of the bus 2 of the CPU is written in the specific bit of the specified address of the RAM, and data from the register RE is written in a bit other than the specific bit of the address of the RAM through selectors SE2WSE17 and a buffer 3. COPYRIGHT: (C)1982,JPO&Japio

Inventors

  • 👤 Shinichi Isobe
  • 👤 Mikio Yonekura

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-05 11:10
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/05; G05B19/054; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G05B2219/00; G05B2219/30; G05B2219/34; G05B2219/34291

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